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Advanced Signal Integrity Technology From Altera
By CXOtoday Staff
Mumbai, Feb 14, 2007
The Electronic Design Automation (EDA) partners will market Altrea's Pre-emphasis and Equalisation Link Estimator (PELE) technology to electronics designers.
PELE will estimate signal integrity settings in Altera's Stratix II GX FPGAs.
Mentor Graphics Corporation is the first EDA partner to integrate PELE into its tool flow. Originally available only to Altera's internal signal integrity experts, PELE, combined with Mentor Graphics HyperLynx tools, will allow high-speed designers to simulate and predict system performance in a matter of hours.
"Integrating PELE into our EDA partners' design tools is an essential step for customers to accelerate the design of multi-gigabit transceivers and to get a product to market," says David Greenfield, senior director of product marketing for high-end FPGAs at Altera.
Using a MATLAB-based model of the Stratix II GX multi-gigabit transceiver, PELE technology uses extracted or measured frequency-domain characteristics of the customer's serial channels to search for optimal signal-integrity setting estimate for all channel characteristics. This eliminates guesswork when determining signal-integrity settings for Stratix II GX FPGAs, to integrate up to 20 low-power transceivers to operate between 600 Mbps and 6.375 Gbps.
"The combination of HyperLynx and Altera's PELE technology provides our mutual customers with leading-edge tools to design their most advanced systems," states Dan Boncella, director of marketing, Mentor Graphics Corporation.
"These capabilities enable users to optimize system performance while reducing their design cycle times", claims Boncella.
The design tools allows users to extract frequency-domain S-parameter characteristics of high-speed interconnects from circuit board and backplane layouts, such as the new I-Trac backplane system from Molex.
The way Altera's PELE technology is embedded into Mentor's design flow ensures file compatibility. PELE imports frequency-domain S-parameter files from HyperLynx or customer measured data, and configures Mentor's ELDO analog simulator directly, to improve productivity and decrease design risk. Users can take the Stratix II GX ELDO-model outputs and predict a bit error rate (BER) and eye opening over hundreds of billions of bits.
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