Confirma platform, a high performance verification solution launched by Synplicity, provider of software for design and verification of semiconductors, aims to improve the traditional ASIC and ASSP verification process.
According to the release, the solution includes Synplicity's Certify tool for multi FPGA partitioning and implementation along with the recently introduced Identify Pro software with TotalRecall technology. It also includes HARDI ASIC Prototyping System (HAPS) FPGA-based prototyping hardware, a flexible prototyping boards.
Certify tool is for ASIC/ASSP prototyping using multiple FPGAs. It combines RTL multi-chip partitioning with best-in-class FPGA synthesis. Using the Certify makes FPGA-based prototyping easier, shortens prototype development time, improves prototype performance, and enables faster time-to-market.
Identify Protocol is a new ASIC and ASSP verification solution, featuring Synplicity's TotalRecall technology. It provides designers with full visibility into FPGA-based ASIC and ASSP prototypes thereby enabling users to find, fix and verify functional errors at speeds approaching that of the real chip. It also improves the productivity of existing verification methodologies, such as assertion-based verification, simulation and emulation.
HAPS provide high speed, high capacity, real-time debugging and full ASIC functionality for ASIC prototyping designers. HAPS boards give designers virtually the same functionality as the ASIC, at speeds approaching that of the ASIC.
Juergen Jaeger, senior director, ASIC verification marketing at Synplicity said, "The Confirma platform allows designers to approach verification differently. Synplicity is positioned to address, for the first time, all the major steps needed to successfully leverage the performance of FPGA-based prototypes as a viable and productive ASIC and ASSP verification solution, from implementation to at-speed execution and debug of the design under test. The Confirma platform makes prototyping easy to use and productive."
Confirma's modular and scalable architecture deploys prototypes as replicates, reducing overall system verification time for software developers and systems integrators by enabling them to run actual software applications. The solution aims to take FPGA-based prototyping to the next usability and productivity level by transforming it into tightly integrated, comprehensive at-speed verification.
