IBM Emblazons Its Self Assembly Nanotechnology
IBM today unveiled the first application for self-assembling nanotechnology to conventional chip manufacturing.
It has used a natural pattern process to create insulating vacuums around nano scale wires, packed next to each other in every computer chip.
This patented process enables compounds to assemble in a directed manner, creating trillions of uniform, nano-scale holes across an entire 300 millimeter wafer. The holes are 20 nanometers in diameter, up to five times smaller than the most advanced lithography technique. Once the holes are formed, the carbon silicate glass is removed, creating a vacuum between the wires -known as the airgap- allowing the electrical signals to either flow 35% faster, or to consume 15% less energy.
Airgaps is a misnomer, as the gaps are actually a vacuum, absent of air. The technique deployed by IBM causes a vacuum to form between the copper wires on a computer chip, allowing electrical signals to flow faster, while consuming less electrical power.
A vacuum insulates wiring capacitance, which occurs when two conductors, in this case adjacent wires on a chip, sap or siphon electrical energy from one another, generating undesirable heat and slowing the speed at which data can move through a chip.
Until now, chip designers often were forced to fight capacitance issues by pushing more power through chips, creating, in the process, a range of other problems. They have also used insulators with better insulating capability, but they become tenuously fragile as chip features get smaller and smaller, and their insulating properties do not compare to those of a vacuum.
The self-assembly process has already been integrated with IBM’s state-of-the-art manufacturing line in East Fishkill, New York and is expected to be fully incorporated in its manufacturing lines and used in chips by 2009. The chips will be used in server product lines, and thereafter for chips IBM builds for other companies.
“This is the first time anyone has proven the ability to synthesize mass quantities of these self-assembled polymers and integrate them into an existing manufacturing process with great yield results,” said Dan Edelstein, IBM fellow and chief scientist of the self-assembly airgap project. “By moving self assembly from the lab to the fab, we are able to make chips that are smaller, faster and consume less power than existing materials and design architectures allow.”
Today, chips are manufactured with copper wiring surrounded by an insulator, which involves using a mask to create circuit patterns by beaming light through the mask and later chemically removing the parts that are not needed. The new technique skips these processes.
It can be incorporated into any standard CMOS manufacturing line, without disruption or new tooling. The self assembly process was jointly invented between IBM’s Almaden Research Center in San Jose, California and the T.J. Watson Research Center, Yorktown, New York. The technique was perfected for future commercial production at the Nanoscale Science and Engineering College of the University at Albany, a research and development site in Albany, New York; and at IBM’s Semiconductor Research and Development Center in East Fishkill, New York.
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