IBM Stacks Chips to Save Power and Time
IBM has devised a three- dimensional semiconductor design, where different functions of a chip are stacked one on top of the other, instead of side by side. The technology is called 3D Stacking.
In 2D designs, the chips sit net to one another horizontally or side by side.
Dr Daniel Dias, director, IBM India Research Laboratory explains, “The technology that makes it possible is known as through silicon vias (TSV)’. Instead of using metal wires to interconnect various chips at the heart of today’s electronic devices, TSV allows chips to communicate through tiny holes drilled directly into the silicon.”
With a three dimensional stacked approach, the distance the data needs to travel on the chip itself is 1000 times less than traditional 2D designs. The reduced distance equates to increases in the speed that data can travel as it executes various functions on the chip. At the same time, since the data can get around more efficiently, it requires less power to perform the same functions. With power consumption costs an increasingly important financial consideration, energy savings from 3D chip stacking technology is an important benefit. As a result, the technique could bring about electronic devices that are smaller, more powerful and consume less battery power.
Dias informs that some chip- makers already stack processors, but connect them with long wires wrapped around the edges of the chips. Others set chip pairs side by side on a circuit board. By etching holes straight through the processors, IBM can use wires one-thousandth as long, and use 40 percent less electrical power.
“Memory and processor chips are often spaced inches apart from each other, causing a lag in transmission as chipmakers multiply the number and voracity of calculating cores on their processors. Slowdowns crop up when data- hungry processors cannot retrieve data fast enough from memory to perform their increasingly complex functions,” maintains Dias.
In IBM’s solution, two chips are sandwiched on top of one another - the distance between them measured in microns, or millionths or a meter- and held together by vertical connections that are etched in silicon holes filled with metal.
Dias says that the TSV technology is currently running in the manufacturing line as the company tests the process and makes it manufacturing ready. “Plans are also in place for clients to begin sampling this technique in the second half of this year. Full scale production is planned for 2008.”
The first application of TSV will be in wireless communications chips that will go into amplifiers for wires LAN and cellular applications. 3D technology will also be applied to a wide range of chips including those running now in IBM’s high-performance server and supercomputing chips that power the world’s business, government and scientific efforts, he adds.
IBM researchers have been working on 3D stacking technology for more than a decade at the T J Watson Research Center and other labs across the world. The Defence Advanced Research Project Advisory (DARPA) has supported IBM in development of tools and techniques for extending chips to the third dimension to drive better performance and new applications of chip technologies.
“Infact, this is the fifth major chip breakthrough in five months from IBM, as it leads the industry in its quest for new materials and architectures to extend Moore’s Law,” Dias concludes.
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